; Asynchronous Single-Line Controller diagnostic (D434B). ; Parameter 1 = path to diagnostic tape. ; ; Configuration locations: ; ; Location Default Value Contents ; ------------- ------------- -------------------------------------- ; DB+0 023434 000000 Switch Register setting ; DB+1 023435 077000 Section Select Register setting ; DB+2 023436 020104 Version update ; DB+3 023437 000022 Interface DRT number ; DB+4 023440 000310 Maximum number of errors ; DB+5 023441 000003 Clock DRT number echo echo echo ------------------------------------------- echo D434B - Asynchronous Single-Line Controller echo ------------------------------------------- echo echo Loading the stand-alone loader. ; Cold load the I/O diagnostics tape. attach -r MS0 %130000-11017_Rev-2640_IO.tape boot MS0 ; Load the tape file containing the diagnostic. ; ; The I/O tape contains these files: ; ; DIAGNOSTIC FILE REV %FILE ; ------------------- ------ ----- ---- ; SLEUTH PD411A 01.05 (01) ; CART DISC-7905A PD419A 01.04 (02) ; MEMORY PATTERN PD421A 01.00 (03) ; MULTIPLEXOR CHAN PD422A 01.02 (04) ; DISC FILE-2888A PD423A 01.00 (05) ; CART DISC-7900A PD424A 01.00 (06) ; SYSTEM CLOCK II/III PD425A 01.00 (07) ; SYS CLK/FLI III-LC PD426A 00.00 (10) ; TERMINAL DATA PD427A 01.01 (11) ; FIXED HEAD DISC PD428A 01.00 (12) ; SELECTOR CHAN PD429A 01.01 (13) ; FLT.CORR.MEM SER-II PD430A 01.01 (14) ; FLT.CORR.MEM SER-III PD430B 00.00 (15) ; EXTEND INSTRUC SET PD431A 01.00 (16) ; HSI DIAG. PD432A 01.00 (17) ; MAGNETIC TAPE PD433A 01.04 (20) ; SSLC INTERFACE PD434A 01.03 (21) ; ASLC INTERFACE PD434B 01.04 (22) ; UI DIAG PD435A 01.01 (23) ; TERMINAL CONTROL PD438A 01.00 (24) ; CALCOMP PLOTTER PD439A 01.01 (25) ; COBOLII A F/W DIAG PD441A 00.00 (26) ; COBOLII B F/W DIAG PD442A 00.00 (27) ; STAND ALONE DISC SADUTIL 01.00 (30) deposit SWCH 22 ; Set the CLK into real-time mode for the timing tests. ; ; Set the SSLC into diagnostic mode to simulate attaching the 30055-60009 ; test connector. set CLK REALTIME set SSLC DIAGNOSTIC,ASYNCHRONOUS ; Load and start the diagnostic. ; ; The diagnostic loads from tape and then waits for a . echo echo Loading and executing the diagnostic. reply "\r" delay 2 seconds go ; Verify HALT 6 and respond to P10 ENTER SWITCH REG. OPTIONS. assert CIR=030366 ; PATCH: This fixes a bug in Section 4 Step 130. It changes ADDI 0 to TSBC 5. ; The unpatched diagnostic reports E325 NO INTERRUPT IN STEP 130. The ; diagnostic sets , then ; does , then sends SYN, SYN, SYN, SYN, SYN, 'U' and ; wants to see a PE interrupt after the 'U'. But SYN is odd and 'U' is ; even. The patch configures for odd parity. deposit 00.014132 TSBC 5 ; PATCH: This fixes a bug in Section 5 Step 152. It changes ZERO,NOP to LOAD ; P+7. The unpatched diagnostic reports: ; ; E328 STATUS ERR IN STEP 152 ; STATUS IS 0 110 110 001 000 011 ; SHOULD BE D DDD D0D DDD DDD DDD ; ; The diagnostic sets associates SOH with Device End, does a 2-word ; packed read, then sends SYN, NUL, SOH, leaving status as 1st byte. ; But the diagnostic wants to see 2nd byte. The patch changes the ; expected status from 1st byte to 2nd byte. deposit 00.013750 LOAD P+7 ; PATCH: This fixes a bug in Section 6 Step 179. It changes the expected status ; from %144003 to %144103. The unpatched diagnostic reports: ; ; E328 STATUS ERR IN STEP 179 ; STATUS IS 1 100 100 001 000 011 ; SHOULD BE 1 100 100 000 000 011 ; ; The diagnostic does a read that ends with associate actions Device End ; and Disable SR, then does Clear Receiver, then does End with ; Interrupt, and then does DSTATSTB. It wants the Association bit to be ; clear. But the P RESET REC signal clears the SYNC flip-flop (so Q ; output is low), and resets the association action latch (so all not-Q ; outputs are high). Schematic sheet 6 shows that the not-Q4 output is ; ANDed with the SYNC flip-flop Q output, producing a low input to gate ; U105B, which produces a low output to the NOT input of the status ; register buffer. Therefore, issuing Clear Receiver sets the ; Association bit. The patch changes the state of the Association bit ; to the correct expected value. deposit 00.013270 144103 ; Set the Switch Register options: ; ; + bit 0 = select the external switch register ; + bit 1 = modify the Section Select Register ; bit 2 = not used ; bit 3 = not used ; bit 4 = not used ; bit 5 = loop on the current section ; bit 6 = not used ; bit 7 = output to the line printer (if configured) ; bit 8 = not used ; bit 9 = suppress non-error messages ; bit 10 = suppress error messages ; bit 11 = loop on the last step ; bit 12 = halt on error ; bit 13 = halt at the end of each step ; bit 14 = halt at the end of each section ; bit 15 = halt at the end of each diagnostic pass deposit SWCH 140000 echo echo Configuring the switch register. echo Expect halt 5 if successful. echo go ; Verify HALT 5 and respond to P11 ENTER SECTION SEL. OPTION. assert CIR=030365 ; Set the Section Select options: ; ; bit 0 = reconfigure ; + bit 1 = execute Section 1 ; + bit 2 = execute Section 2 ; + bit 3 = execute Section 3 ; + bit 4 = execute Section 4 ; + bit 5 = execute Section 5 ; + bit 6 = execute Section 6 ; bit 7 = execute Section 7 ; bit 8 = execute Section 8 ; bit 9 = not used ; bit 10 = not used ; bit 11 = not used ; bit 12 = not used ; bit 13 = not used ; bit 14 = not used ; bit 15 = not used deposit SWCH 077000 echo echo Configuring the section select register. echo Expect halt 6 if successful. echo go ; Verify HALT 6 and respond to P10 ENTER SWITCH REG. OPTIONS. assert CIR=030366 ; Set the Switch Register options: ; ; + bit 0 = select the external switch register ; bit 1 = modify the Section Select Register ; bit 2 = not used ; bit 3 = not used ; bit 4 = not used ; bit 5 = not used ; bit 6 = not used ; bit 7 = output to the line printer (if configured) ; bit 8 = not used ; bit 9 = suppress non-error messages ; bit 10 = suppress error messages ; bit 11 = loop on the last step ; + bit 12 = halt on error ; bit 13 = halt at the end of each step ; bit 14 = halt at the end of each section ; + bit 15 = halt at the end of each diagnostic pass ; ; NOTE: If bit 9 is set, this diagnostic does not halt at the end of each pass ; but instead loops continuously, even though bit 12 is set. deposit SWCH 100011 ; Run the diagnostic. echo echo Reconfiguring the switch register and executing the diagnostic. echo Expect halt 15 for successful completion. go ; End the of diagnostic. ; ; Verify HALT 15 for a successful pass. assert CIR=030375 ; Restore the hardware configuration. set CLK CALTIME set SSLC SERIAL,SYNCHRONOUS